Sacramento, California - 916-868-1423
IC MASK DESIGNER (DIGITAL OR ANALOG)
Ten Years of experience in floorplanning, datapath planning, and layout assembly.
Extensive training in planning and creating quality, reliable circuits that meet timing,
width, shielding, electro-migration, and self heating requirements
Experience in the layout of analog circuitry such as capacitors, resistors, diodes,
and various transistors as well as digital logic devices.
Tool Proficiencies:
- Cadences' Virtuoso and Virtuoso XL Layout Tool
- Mentor Graphics' Calibre LVS/DRC verification tool
- Genesys layout tool
- Silvaco's Expert layout tool
- Silvaco's Guardian layout verification tool
- Hercules LVS/DRC verification tool
- CHPR and Galaxy
- Intermediate level Unix/Linux OS navigation and commands
- Microsoft Windows and Office
PROFESSIONAL EXPERIENCE
SUN MICROSYSTEMS, Sunnyvale,
California October 2005 - January 2005
Layout Designer
Layout of a variety of digital blocks of varying complexity including SRAM's, Registers, Data Queues, Instruction
Queues, etc. Was required at times to multitask and support up to 3 separate blocks. Brought schedule in significantly
on several blocks that I supported.
Key Contributions:
-
Ramped up on design process within a week.
-
Brought schedule for STT block in by several weeks. Implemented additional changes that were scheduled
for 2nd circuit revision.
-
Drew ARCH_REGS block over a course of 8 days. Ahead of schedule by a couple of weeks.
-
Drew 75% of 64 bit SRAM block within 2 weeks. Engineer had not created schematics for remaining 25%
-
Drew SRAM r/w drivers with multiple design restrictions. These restrictions had caused other similar
designs to grow because it "couldn't be done".
-
Modified data buffer design
to reduce previously drawn long M1 usage by 75%
JSI MICROELECTRONICS,
McClellan,
California
May 2005 - October 2005
Analog Layout Designer
Performed layout design of the entire analog chip, including setup of Silvaco's Expert tool and the design process parameters.
Duties included block and pad placement, analog circuit layout, schematic entry, DRC checks, netlist creation, and LVS checks.
Also worked with process fabrication company to verify and correct design guidelines.
Key Contributions:
- Successfully resolved all tool functionality issues with tool and process vendors.
- Solely responsible for layout implementation of fab process used. Configured files on Silvaco's Expert tool to correspond
with the design process parameters.
- Assisted engineer in schematic entry on Silvaco's Gateway tool.
- Given almost complete autonomy for completion of layout. I was the sole mask designer for the company.
- Successfully setup and resolved issues
concerning Silvaco's Guardian LVS verification tool.
INTEL CORPORATION, Folsom,
California
September 1995 -
May 2005
IC Layout Designer
Implementation of changes to legacy layout as well as planning and assembly of new layout blocks. Focused
on Pentium microprocessors (II, III, and IV) but also worked on Centrino mobile processors and chipset chips as well.
Led, planned, and implemented large changes that required multiple MD's and several months to finish. Led teams of up
to 15 Mask Designers to assist me in completing the sections assigned.
Led Reliability Verification training for a group of about 20 other designers. Also led same team in cleaning RV
verifications for entire Pentium III chip.
As needed, I functioned as the main contact person for problems encountered with the DLS layout tool. I also had
occasion to use the CHPR and Galaxy tools when needed.
Key Contributions:
- Planned blocks with hundreds of thousands of transistors and led teams of up to 15 people in design and assembly.
- Successfully researched and resolved
hundreds of issues pertaining to design, verification, automation,
and assembly.
EDUCATION AND CREDENTIALS
Associates Degree in Computer Electronics
AMERICAN RIVER COLLEGE
- Sacramento, California
Professional Training and Certifications
CMOS1 Training at AMERICAN RIVER COLLEGE
- Sacramento, California
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